1. Field of the Invention
This invention relates generally to enabling circuitry for logic circuits and, more particularly, to enabling circuitry for transistor-transistor logic (TTL) circuitry which utilizes the clock signal directly rather than after inversion to reduce the enabling delay without an associated power penalty.
2. Description of the Prior Art
Logic circuits such as data latches, flip-flops, shift registers, memories, etc. may require that an enabling signal be applied thereto in order to render the logic circuit operational. For example, the ALS377 hex data latch manufactured by Motorola Inc. requires the presence of such a signal.
Prior art enabling circuitry requires that an external clock signal (CK) propagate through three gates before the required enabling signal is produced. Thus, the enabling of the particular logic circuit involved is delayed by the propagation delay of the three gates. If the clock signal could be used directly rather than requiring inversion in the first of the three gates, there could be a significant improvement in enabling time.